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A reader named Anand suggested diagrams for the scan test basics article. I’m happy to oblige. Read the rest of this entry »

The target audience for this article is digital system designers or students who are unfamiliar with basic elements of design for test.

The two essential parameters of an effective test with high fault coverage are controllability and observability. Scan test is a means of increasing both in a sequential digital IC design. Read the rest of this entry »

“A hen is only an egg’s way of making another egg.”
Samuel Butler (1835-1902)

It’s always valuable to keep in mind the point of view of your customer, but sometimes we fail to appreciate exactly who the customer is. In chip design, it’s easy to overlook the fact that before the fruits of your labor end up in a computer or an MP3 player or a cell phone, they pass through the hands of another “customer,” an engineer who, if all goes well, you will never meet. Read the rest of this entry »

A great deal of effort is spent in some design teams to achieve high fault coverage test programs in pursuit of enhanced reliability. While this is a laudable goal, one must understand the difference between a fault and a defect to avoid unnecessary and unproductive effort. Read the rest of this entry »

Transistors are formed by diffusing different dopants into silicon in specific patterns. Circuits are formed by connecting transistors to one another with wires. Integrated circuits are single pieces of silicon having many transistors with networks of aluminum or copper traces acting as wires to connect them. The transistors and wires are formed by laying down patterns of different substances, layer upon layer. Read the rest of this entry »