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The target audience for this post is digital system design engineers; knowledge of digital design is assumed.

What are clock domains?

When they first became an issue, clock domain crossings (CDCs) were determined by the inability of static timing analysis (STA) tools to determine the timing relationship between two individual signals. To a certain extent, that’s still true. The problem is one of scale. When you only had one clock, the problem did not exist. When you had two or three clocks, the problem was manageable as a small number of exceptions. When you have dozens or hundreds of clocks, CDCs are no longer exceptions; there are just too many of them.¬† Read the rest of this entry »

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For anyone involved in supporting customers of any non-trivial commercial software product, it is very important to understand the distinction between a product demo and product training.

Ideally, demos are pre-sales and training is post-sales. Read the rest of this entry »

A reader named Anand suggested diagrams for the scan test basics article. I’m happy to oblige. Read the rest of this entry »

One of the highest-traffic articles I’ve written for this blog is Scan Test Basics. It seems fitting to review that article and add a few more thoughts on this topic.

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A blog post by Matt (who, I’ve just noticed, posts his picture but not his last name in his blog) seems similar to something I’ve been saying for a number of years, that EDA GUIs are not designed, they grow. These are tools intended for use by other engineers, and they still suffer from the same points Matt lists. Enjoy!

The process of designing chips starts with the construction of a computer model based on the design specification. The computer model is used to derive both masks and test programs used in the manufacturing process. Some people not intimately familiar with the process are dismayed to learn that the testing process, and indeed the test environment, almost never replicate the way the chip will be used in the final product. Here’s why this is not a problem. Read the rest of this entry »

Computer simulations, such as those used in the design of semiconductor integrated circuits, make it possible to design these circuits at a reasonable cost, but like all simulations they have their limitations. One of the most important things to realize about computer simulations it that they cannot predict success; they can only predict failure. A simulation that “passes” actually fails to predict a failure, and the best that can be said is that possible failure modes covered by the simulation have been eliminated. The more detailed the simulation, the more failure modes can be covered, but the longer the simulation takes to run.¬† If the level of detail is too great for the size of the design, the model won’t fit into the computer memory at all. Read the rest of this entry »

The target audience for this article is digital system designers or students who are unfamiliar with basic elements of design for test.

The two essential parameters of an effective test with high fault coverage are controllability and observability. Scan test is a means of increasing both in a sequential digital IC design. Read the rest of this entry »

“A hen is only an egg’s way of making another egg.”
Samuel Butler (1835-1902)

It’s always valuable to keep in mind the point of view of your customer, but sometimes we fail to appreciate exactly who the customer is. In chip design, it’s easy to overlook the fact that before the fruits of your labor end up in a computer or an MP3 player or a cell phone, they pass through the hands of another “customer,” an engineer who, if all goes well, you will never meet. Read the rest of this entry »

A great deal of effort is spent in some design teams to achieve high fault coverage test programs in pursuit of enhanced reliability. While this is a laudable goal, one must understand the difference between a fault and a defect to avoid unnecessary and unproductive effort. Read the rest of this entry »