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The target audience for this post is digital system design engineers; knowledge of digital design is assumed.

What are clock domains?

When they first became an issue, clock domain crossings (CDCs) were determined by the inability of static timing analysis (STA) tools to determine the timing relationship between two individual signals. To a certain extent, that’s still true. The problem is one of scale. When you only had one clock, the problem did not exist. When you had two or three clocks, the problem was manageable as a small number of exceptions. When you have dozens or hundreds of clocks, CDCs are no longer exceptions; there are just too many of them.  Read the rest of this entry »

A reader named Anand suggested diagrams for the scan test basics article. I’m happy to oblige. Read the rest of this entry »

One of the highest-traffic articles I’ve written for this blog is Scan Test Basics. It seems fitting to review that article and add a few more thoughts on this topic.

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The target audience for this article is digital system designers or students who are unfamiliar with basic elements of design for test.

The two essential parameters of an effective test with high fault coverage are controllability and observability. Scan test is a means of increasing both in a sequential digital IC design. Read the rest of this entry »

“A hen is only an egg’s way of making another egg.”
Samuel Butler (1835-1902)

It’s always valuable to keep in mind the point of view of your customer, but sometimes we fail to appreciate exactly who the customer is. In chip design, it’s easy to overlook the fact that before the fruits of your labor end up in a computer or an MP3 player or a cell phone, they pass through the hands of another “customer,” an engineer who, if all goes well, you will never meet. Read the rest of this entry »

A great deal of effort is spent in some design teams to achieve high fault coverage test programs in pursuit of enhanced reliability. While this is a laudable goal, one must understand the difference between a fault and a defect to avoid unnecessary and unproductive effort. Read the rest of this entry »

A common practice in the EDA industry is to assign the task of teaching classes to applications engineers. At first blush, this makes sense, since the job of the applications engineer is to deal directly with customer engineers. However, there is a difference between dealing one-on-one and being in charge of a classroom. Read the rest of this entry »