Computer simulations, such as those used in the design of semiconductor integrated circuits, make it possible to design these circuits at a reasonable cost, but like all simulations they have their limitations. One of the most important things to realize about computer simulations it that they cannot predict success; they can only predict failure. A simulation that “passes” actually fails to predict a failure, and the best that can be said is that possible failure modes covered by the simulation have been eliminated. The more detailed the simulation, the more failure modes can be covered, but the longer the simulation takes to run.  If the level of detail is too great for the size of the design, the model won’t fit into the computer memory at all.

The solution to this problem is to eliminate certain details to reduce model size and run time. This is known as raising the level of abstraction. In a way, it’s like the Russian babushka dolls, nested within one another, except that it’s the inner-most doll that is the most detailed. Whenever increased design size makes the level of detail too much for our simulator to handle, we wrap another doll, or level of abstraction, around it to hide the details inside.

The lowest level of abstraction I know of in chip design is known as semiconductor process simulation, which analyzes doping distributions and process geometries. Process simulation results are used to create semiconductor device models or transistor models. These models are used in SPICE simulations, which is the next higher level of abstraction.

SPICE stands for Simulation Program with Integrated Circuit Emphasis and is one of the oldest semiconductor simulation programs; it was developed at the University of California, Berkeley in the early ’70s. SPICE is an analog simulator, so the results, at least in terms of voltage vs. time, are analog waveforms. In digital circuits, transistors are combined into logic gates and storage elements, and corresponding transistor models can be combined and simulated in SPICE. The SPICE simulation results from these logic elements are used to create the appropriate models for so-called gate level simulations.

The output of a gate level simulation is not analog, but digital, showing only 1’s and 0’s. The transition from SPICE to gate level is an excellent example of a rising level of abstraction. It’s easy to see the great loss of detail in going from an analog waveform to a digital waveform. It’s also easy to appreciate the great gain in capacity. The practical limit of a SPICE simulation is dozens or perhaps hundreds of transistors. Gate level simulations can be used for tens of thousands of gate equivalents, where the standard conversion factor is four transistors for each gate equivalent, far beyond the practical limit for SPICE.

However, in a world where state of the art chips have millions of gates, gate level simulations in turn become impractical. Thus was born Register Transfer Level, or RTL simulation. In RTL, everything between registers is abstracted to one degree or another. Instead of representing each logic gate in, say, an adder or a multiplier, RTL simulation just says A + B or A * B, along with an appropriate delay which may be derived from a gate level simulation. This delay is for the entire result, and doesn’t make any distinction between the delays of the individual bits that you would see with a gate level simulation. Once again, detail is lost, capacity is gained, and data from the previous level is used to specify the higher level.

In terms of physical design and timing analysis, it is necessary to traverse back down the abstraction levels in order to create masks. This process is largely automated, from synthesis to place-and-route to parasitic extraction. But the levels of abstraction are still there.

The two main hardware description languages used in RTL are Verilog and VHDL. These are, in effect, programming languages not terribly unlike other familiar languages such as C or Fortran. The difference is that hardware description languages lend themselves to logic synthesis, that is, deriving logic gates and hence transistors, and thereby expressing the coded algorithms as hardware rather than software. As with any EDA technique, the goal is to enable hardware functions to be automatically generated by a software program, rather than using the old painstaking method of designing chips one transistor at a time.

The next logical step in producing an even higher level of abstraction would be to eliminate the RTL middleman and derive hardware directly from a programming language such as C or C++. That is the goal of ESL, or Electronic System Level design. As with previous levels of abstraction, the initial implementations of ESL seek to convert C++ programs to RTL, just as synthesis converts RTL to gate level, thus adding yet another link to the existing chain of abstraction levels.

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